| Clock | Target Period (ns) | Worst Negative Slack (WNS) | Worst Hold Slack (WHS) | Status | |-------|--------------------|----------------------------|------------------------|--------| | clk_100MHz | 10.000 | 1.245 ns (MET) | 0.089 ns (MET) | PASS | | clk_div_10MHz | 100.000 | 12.345 ns (MET) | 0.034 ns (MET) | PASS |
(Insert a block diagram showing top-level ports and major internal modules) vivado design